Private beta · Spring 2026

The proving ground for analog chip designers.

Run real SPICE simulations with open-source EDA tools in your browser. Submit your designs and climb a leaderboard where students and working engineers compete on the same problems — scored deterministically.

No spam. We'll email you when your spot opens.

Open-source EDA tools

30+

Graded challenges

SKY130 · ASAP7

PDKs ready

01 · Leaderboard

A ranked record of who can actually design the circuit.

Every submitted netlist is simulated on our backend against the same testbench. Scores are deterministic. Reputation is earned, not claimed.

Rank	Designer	Role	Score	Progress	Solved

Example view · waitlist open Season 1 launching summer 2026

> deterministic

Same testbench for everyone

Each challenge has a fixed testbench and grading rubric. No hand-waving, no vibes — your score reflects measured performance.

> verifiable

Every run is reproducible

Submission artifacts — netlist, simulation log, measurement file — are preserved per run, so graders and recruiters can audit your work.

> recruitable

Build a portfolio that speaks

Your rank, your solved challenges, and your best netlists become a public profile companies can actually evaluate on technical merit.

02 · Console

A real Linux terminal. With every tool you need, pre-installed.

ngspice, OpenROAD, yosys, iverilog, magic, klayout, netgen — plus Python, vim, git. Not a sandboxed demo. A workspace you can actually design in.

> real

Not a toy emulator

Full Linux containers on AWS Fargate. Install packages, run scripts, use Python notebooks — the same workflow you'd have at a tape-out team.

> persistent

Your workspace survives

Projects, netlists, and results persist across sessions. Pick up where you left off. Share a workspace snapshot with a teammate.

> submit

One command to rank

When your design passes local checks, chiprank submit runs the official testbench and posts your score.

03 · How it works

From sign-up to leaderboard in one session.

STEP 01

Pick a challenge

Browse the catalog — current mirrors, bandgap references, two-stage OTAs, LNAs, PLLs. Each has a spec, a testbench, and a grading rubric.

STEP 02

Design in the console

Write your netlist in the browser terminal. Run ngspice, sweep corners, iterate. Your workspace persists between sessions.

STEP 03

Submit & rank

One command runs the official testbench on our infrastructure and posts your score. Climb the leaderboard. Build a portfolio.

The proving ground for analog chip designers.

A ranked record of who can actually design the circuit.

A real Linux terminal. With every tool you need, pre-installed.

From sign-up to leaderboard in one session.

Design, simulate, rank.